An Approach for CMOS based DADDA Multiplier Design
Abstract- In this paper design and analysis of CMOS based DADDA multiplier proposed, multiplier is important circuit in arithmetic logic unit. Currently in portable electronics devices low power multiplier required to design. Multipliers are the major source of power dissipation in digital electronics circuit. DADDA multiplier CMOS based design enhanced the performance in term of power consumption, area, and delay comparatively to other multiplier design. DADDA algorithm reduces summation of partial products stage and in implementation of DADDA multiplier number of adder required minimizes. The simulation is done by using TENNER EDA tool.
Keywords: DADDA Multiplier, Full Adder, Half Adder ,Ripple carry Adder, low power
1. INTRODUCTION
Multiplication is backbone of arithmetic operation, which is play major role in many VLSI system such as microprocessor and digital signal processor .Multiplication is arithmetic operation which performed by multiplier, multiplier is a combinational circuit which designed by different algorithm approach .Them major consideration while designing multipliers is power dissipation.In1964 wallance introduced a multiplier with combination of half adder and full adder .Later Luigi DADDA invented parallel multiplier during 1965 with combination of half adder and full adder DADDA Multiplier better than to other multiplier because of less hardware requirement ,easy layout, high speed low power consumption..
1.1 Multiplier: definition
A digital circuit which use to perform multiplication of binary number. In multiplier most techniques involve computing a set of partial product is generated by multiplying the multiplicand with a bit of the multiplier, multination operation shown in figure. This structure shows three function of multiplication: partial product, partial product accumulation, final addition 1
Fig. 1Binary Multiplication
A. Partial product generation
Partial Product Perform By Using Logical AND Of Multiplicand X Bit With Multiplier Bit Y And Number Of AND Gate Required N 2 To Formed Partial Product Matrix .Partial Product AND Gate Matrix Design Using CMOS As Shown In Figures
Fig. 2 Schematics Of AND GATE Cell
Fig. 3 Partial product Matrix AND Gate schematics
B. Partial product accumulation
Multiplication operation performs by accumulated partial product using half Adder and Full Adder. Dadda, reduction minimize the number of stage required to perform the operation the summation of partial product.
Fig. 4 Partial Product Summation Schematics View By Dadda algorithm
C. Final Addition
This function performs after partial product accumulation by grouping of two numbers and adds them with a conventional adder. In this proposed work ripple carry adder used, a logical circuit using multiple full adder input a cin , which is the output of previous adder ,This kind of adder is called ripple carry adder, since each carry bits ripple to next adder. Only that first full adder is replaced by a half adder by under assumption that cin = 0 .
Fig 5 ripple carry adder schematic
2. DADDA MULTIPLIER:
The DADDA scheme is one of the parallel multiplier schemes that essentially minimize the number of adder stages required to perform the summation of partial products. This is achieved by using full and half adders to reduce the number of rows in the matrix number of bits at each summation stage. Dadda succeeded this, by placing the 3,2 and 2,2 counters in maximum Critical path in optimal manner. For an N-bit multiplier and multiplicand, there results a N by N partial products. These partial products are arranged in the form a Matrix. Dadda reduced these Matrix height to a two-rowed matrix, through a sequence a reduction stage2.
A. Algorithm:
1. Let, us assume the final two-rowed matrix height d1 = 2, based on d1 the successive matrix heights are obtained from dj+1 = 1.5 * dj , where j = 1,2,3,4,…………, Rounding of fraction in this matrix height should be done down to least. i.e, 13.5 = 13(rounded). The matrix heights will be in this fashion 2,3,4,6,9,13,19,28…………. Finally the largest dj should be obtained such that derived matrix height shouldn’t exceed the Matrix overall height.
2. In the first reduction stage, the column compression is to carried with the 3,2 and 2,2 counters such that the obtained reduced matrix height should not exceed dj.
3. During the compression, the sum is to be passed to same column in the next reduction stage and the carry is to be passed to the next column.
4. The above two steps are to be repeated until a final two-rowed reduced matrix is obtained.
B. Implementation
In Dadda implementation, in general, the number of full adders required is N2-4N+3 and the number of half adders is always N-1.
a3 a2 a1 a0
15
a3b3 11
a2b3 7
a1b3 3
a0b3 b3
14
a3b2 10
a2b2 6
a1b2 2
aob2 b2
13
a3b1 9
a2b1 5
a1b1
1
aob1 b1
12
a3b1 8
a2b0 4
a1b0 0
a0b0 b0
Fig. 6. Table Input data(muktiplicand ; multiplier)
Fig. 7 Reduction of The partial product by Dadda approach3
C. Flow Chart
Fig. 8 Flow chart of implenmentation of Dadda multiplie
3. 4*4 BIT DADDA MULTIPLIER
In this schematcs view dadda multiplier divided in three part,first part shows partial product generation symbol view,second part shows reduced partial product summation symbol view ,third part shows final addition symbol view .
Fig. 9 4*4bit Dadda Multiplier Schematics View
A. Partial product generation symbol view
In dadda multiplier to perform partial product operation AND Gate Matrix design using CMOS ,this AND Gate matrix generate a product of multicand X bit with multiplier y bit.In this symbol view shows4*4 bit partial product, multiplicand a0,a1,a2,a3,a4 bit and multiplier b0,b1,b2,b3 bit.
Fig. 10 Partial Product Matrix AND Gate symbol View
B. Partial Product accumalatio symbol view
This symbole view perform operation of Partial product summation by half adder and full adder number of fulladder (N 2-4N+3), half adder (N-1) required in Dadda multiplier design.Each stage of adder output is input of next stahe of adder as shown figure 11.
Fig. 11 Partial Product matrix symbol and Schematic view
D. Final Addition schematic view
This schematics view shows final addition operation of Dadda multiplier by using ripple carry adder ,full adder uses to design ripple carry adder .each full adder output carry is input of next stage of full adder ,first full adder cin =04.
s
Fig. 12 ripple carry adder schematic view
Half adder:
This schematics view of Half adder, it is design by AND Gate and XOR Gate as shown in figure13.
Fign 13 Schematicsview of half adder
XOR Gate:
This schematics view of XOR Gate, it is design by CMOS as shown in this figure14
Fig.14 schematics view XOR schematics
OR Gate:
This schematics view of OR Gate , it is design by CMOS as shown in figure15.
Fig. 15 schematics view of OR Gate
Full Adder:
This schematics view of Full adder, it is design by two Half adder and OR Gate as shown in figure16.
Fig.16 Schematics view of Full Adder
Inverter:
This schematics view of inverter , it is design by CMOS as shown in figure17.
Fig17 Schematics view Of Inverter
Waveform of 4*4 Bit Dadda Multiplier:
This figure shows operation of dada multiplier in terms of wave form down to up waveform order is as i/p, out0, out1, ouit2, out3, out4, out5, and out6 and out7 waveform. Input waveform shows 1010101010 bit when input bit is 1 means all input of 4*4 dadda multiplier input is a0a1a2a3 =11111, b0b1b2b3 =1111, and output is Out0 out1, out2, out3, out4, out5, out6, out7=1110001, similarly i/p = 0 means a0a1a2a3 =0000, b0b1b2b3 =0000 and output =00000000bit.
Fig.18 Waveform Of 4*4bit Dadda Multiplier
5. CONCLUSION
In This Paper Dadda Algorithm Approach Presented to Design Multiplier Dadda in order reduce the hardware which ultimately reduces power and area ,energy efficient basic modules AND Gate ,Half adder ,Full adder and partial product generate cell have been analyzed. At last stage ripple carry adder are used to implement Dadda multiplier. It is simulated by using TANNER EDA toll.
REFERENCES
1 B.Parhami, “Computer Arithmetic”, Oxford University Press, 2000.
2 Luigi Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, Vol. 34, pp. 349-356, August 1965
3 Navdeep Goel and LalitGarg, “Comparative Analysis of 4-bit CMOS Multipliers”, Proceedings of International Conference on VLSI, Communication ; Instrumentation, pp. 33 – 37, 2011
4 B.Ramkumar, Harish M Kittur and P.Mahesh Kannan, ” ASIC Implementation of Modified Faster Carry Save Adder”, European Journal of Scientific Research, Vol. 42, Issue 1, 2010
5 R.Uma, Vidya Vijayan , M. Mohanapriya, Sharon Paul, “Area, Delay and Power Comparison of Adder Topologies”, International Journal of VLSI design ; Communication Systems, vol.3, No.1,pp.153-168 February 2012.
6 A. M. Shams and M. Bayoumi, “Performance evaluation of 1- bit CMOS adder cells,” Proceedings of IEEE International Symposium Circuits and Systems, Orlando, FL, vol. 1, pp. 27–30, May 1999
7 K.Venkata Siva Reddy, C.Venkataiah, ” Design of Adder in Multiple Logic Styles for Low Power VLSI”, International Journal of Computer Trends and Technology, vol. 3, no.3, pp.476-481, 2012
8 Mariano Aguirre-Hernandez and Monico Linares-Aranda “CMOS Full-Adders for Energy-Effici Arithmetic Applications”, IEEE transactions on VLSI systems, vol. 19, no. 4, pp. 718-721, April 2011
9 J. M. Rabaey, Digtal Integrated Circuits – A Design Perspective. Prentice Hall Press, 2001
10 C. Jaya Kumar and R. Saravanan “VLSI Design for Low Power Multiplier using Full Adder”, European Journal of Scientific Research, vol.72, no.1, pp. 5-16, March 2012.