CHAPTER 1: INTRODUCTION
The main design of the robot consists of a ‘Human Detection Module’ carried by a mobile robot platform sufficiently small enough to wander around the area and carry out its search activity. A unique passive Infrared sensor is used in our design that detects humans. This PIR Sensor is placed on a robot that can move in the earthquake prone areas. As a human body emits thermal radiation it will be received and manipulated by the PIR (Passive infrared sensor). Once a human target is located the system gives an alert which may help to localize the victim location as soon as possible. The robot can be carried to any place in the world and can be assembled in few minutes for fast search and rescue operations. The design is simple with the cheapest budget. The robot is driven on a geared DC motor for increased torque and low speed and stepper motor for increased turning accuracy hence, the price control on position is monitored. The robot consist of a three wheel geared drive with DC motors attached to perform forward and reverse movement.
RECEIVER: In receiver mode, human radiations are received and then decoded into BCD form and given to microcontroller.
Info provider system: With the help of gsm technology, the wireless information is given to hospitality team for proper help.
Robot: In this prototype we have used two motors that operate the robot.
• Components availability.
• How to decide value of components.
• Circuit designing.
• How to do soldering properly.
• Programming of sensor.
• LCD interfacing.
• Circuit designing on proteus software.
• Programming language embedded c and assembly.
• How to use Keil software?
• Generate the hex file.
• How to burn the IC?
PROJECT PROPOSAL METHODOLOGY:
1. Design over all frame script such as
• Idea of project
• Components list
• Circuit diagram
2. Decide the rating of various components.
3. Design a circuit on PCB and assemble the components.
• Use Keil software.
• Code in assembly or embedded C language.
• Create the hex file.
5. Design a circuit diagram on proteus for simulation and try to run simulation on proteus.
6. Use Top-win software and program the IC.
7. Testing tools
• Led indication
1. DC Battery.
2. Capacitors (1000uf,10uf,27pf ,100uf,55uf).
3. Resistors (1k,10k,470ohm,22k,56k).
4. Transistors (npn and pnp).
5. Diodes (in4007).
6. 555 Timer
10. GSM mobile.
11. Hands free
BAT? 1 VI VO 3
PIR SENSOR 12
8 P1.7 P3.7/RD 17
9 RST P0.7/AD7 32
2 4 MOC3022
2 4 MOC3022
NPN D4 BUZ1
CHAPTER 2: LITERATURE REVIEW
2.1 PRINTED CIRCUIT BOARD
Making a Printed Circuit Board is the first step towards building electronic equipment by any electronic industry. Various methods are available for making P.C.B., the simplest method is of drawing pattern on a copper clad board with acid resistant (etchants) ink or paint or simple nail polish on a copper clad board and do the etching process for dissolving the rest of copper pattern in acid liquid.
Printed circuit boards offer advantages like compactness, simplicity of servicing and ease of interconnection. PCBs that are commonly used can be classified as single sided, double sided and double sided with plated-through-hold (PYH)
Boards are made up of two types of material, phenolic paper based material and glass epoxy material. Both materials are available as laminate sheets with copper cladding. Printed circuit boards have a copper cladding on one or both sides. The copper on the boards is about 0.2mm thick and weighs an ounce per square foot. Boards are prepared in sizes of 1 to 5 metre wide and upto 2 metres long. The thickness of the boards is 1.42 to 1.8mm.
2.2 POWER SUPPLY
All digital circuits require regulated power supply. In this article we are going to learn how to get a regulated positive supply from the mains supply.
Figure shows the basic block diagram of a fixed regulated power supply. Let us go through each block.
A transformer consists of two coils namely PRIMARY & SECONDARY windings. They are linked together through inductively coupled electrical conductors also called as CORE. A changing current in the primary causes a change in the Magnetic Field in the core and in accordance to Lenz’s law an alternating voltage in the secondary coil is induced. The secondary voltage of the transformer depends on the number of turns on the primary side as well as on the secondary side.
If load is applied to the secondary then an alternating current will flow through the load. In an ideal condition, all the energy from the primary circuit will be transferred to the secondary circuit through the magnetic field.
A rectifier is a device that converts an AC signal into DC signal. For rectification purpose generally diode is used. A diode is a device that allows current to pass only in one direction i.e. when the anode of the diode is positive with respect to the cathode then only it allows current to flow through it, this condition is also called as forward biased condition and diode blocks current in the reversed biased condition.
Rectifier can be classified as follows:
1.Half Wave Rectifier
This is the simplest type of rectifier consisting of only one diode. When an AC signal is applied to it, during the positive half cycle the diode is forward biased and current flows through it. While during the negative half cycle diode is reverse biased and no current flows through it. Since only one half of the input reaches the output, it is very inefficient to be used in power supplies.
2.Full Wave Rectifier
The full wave rectifier consist of a center tapped transformer i.e. we would have to double the size of secondary winding ; provide connection to the center. Therefore, when AC signal is applied then during the positive half cycle diode D1 conducts and D2 is in reverse biased condition. During the negative half cycle diode D2 conducts and D1 is reverse biased. Thus we get both the half cycles across the load. This makes it more efficient.
One of the disadvantages of Full Wave Rectifier design is the necessity of using a center tapped transformer, thus increasing the size and cost of the circuit. This can be avoided by using the Full Wave Bridge Rectifier.
3.Full Wave Bridge Rectifier
Full Wave Bridge Rectifier consists of four diodes namely D1, D2, D3 and D4. During the positive half cycle diodes D1 and D4 conduct whereas in the negative half cycle diodes D2 and D3 conduct thus the diodes keep switching the transformer connections so we get both the half cycles in the output.
Therefore, it is much more efficient than Half Wave Rectifier and that too without using a center tapped transformer thus much more cost effective than Full Wave Rectifier.
2.2.3 FILTER (CAPACITOR)
Even though half wave ; full wave rectifier give DC output, none of them provides a constant output voltage. For this we require to smoothen the output waveform received from the rectifier. This can be done by placing a capacitor at the output of the rectifier. This capacitor is known as “FILTER CAPACITOR” or “SMOOTHING CAPACITOR” or “RESERVOIR CAPACITOR”. Even after using this capacitor a small amount of ripple will remain.
Vr= Ripple voltage
F= Frequency of the waveform
I= Current flowing through the circuit
(A half wave rectifier has only one peak in one cycle so F=25hz whereas a full wave rectifier has two peaks in one cycle so F=100hz.)
2.2.4 VOLTAGE REGULATOR
A Voltage regulator is a device which converts varying input voltage into a constant regulated output voltage. Voltage regulator can be of two types:
1.Linear Voltage Regulator
In these devices resistance of the regulator varies in accordance with the load resulting in a constant output voltage. Therefore, it is also called as Resistive Voltage regulator because they dissipate the excessive voltage resistively as heat.
In these devices the output voltage is regulated by switching the current ON/OFF very rapidly. Since their output is either ON or OFF, it dissipates very low power thus achieving higher efficiency as compared to linear voltage regulators. But they are more complex and generate high noise due to their switching action. For low level of output power switching regulators tend to be costly but for higher output wattage they are much cheaper than linear regulators.
The most commonly available Linear Positive Voltage Regulators are 78XX series and Negative Voltage Regulators are 79XX series, where the XX indicates the output voltage.
The MC78XX/LM78XX/MC78XXA series of three terminal positive regulators are available in the TO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range of applications. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.
Each type employs internal current limiting, thermal shut down and safe operating area protection, making it essentially indestructible. If adequate heat sinking is
provided, they can deliver over 1A output current.
One can get a constant high-voltage power supply using inexpensive 3-terminal voltage regulators through some simple techniques described below. Depending upon the current requirement, a reasonable load regulation can be achieved. Line regulation in all cases is equal to that of the voltage regulator used.
Though high voltage can be obtained with suitable voltage boost circuitry using ICs like LM 723, some advantages of the circuits presented below are: simplicity,
low cost, and practically reasonable regulation characteristics. For currents of the order of 1A or less, only one zener and some resistors and capacitors are needed. For higher currents, one pass transistor such as ECP055 is needed.
Before developing the final circuits, let us first understand the 3-terminal type constant voltage regulators. Let us see the schematic in Fig. where 78XX is a 3-terminal voltage regulator.
Rectified and filtered unregulated voltage is applied at VIN and a constant voltage appears between pins 2 and 3 of the voltage regulator. The distribution of two currents in the circuit (IBIAS and ILOAD) is as shown.
The figure shows a schematic for obtaining low-voltage regulated output using 3-terminal voltage regulators. It is highly recommended to use the two capacitors as shown. Electrically regulator will be at a distance from the rectifier supply. Thus, a tantalum grade capacitor of 5mf and rated voltage is good. Electrolytic capacitor is not suitable for it as it is poor in response to load transients, which have high frequency components. At the output side a 0.22mf disc ceramic capacitor is useful to eliminate spurious oscillations.
These voltage regulators have a typical bias current of 5 mA, which is reasonably constant. By inserting a small resistor Rx between pin 2 and ground, the output voltage is regulated in many cases. By this method voltage increment of 5 to 10 per cent is practically feasible. However, if a high-value resistance is used to obtain a higher output voltage, a slight variation in bias current will result in wide variation of the output voltage.
Now let us see that what can be done to get a higher but constant output voltage. If to the circuit of Fig.2.7 resistor RY and zener Vz are added as shown in Fig.2.8, then output voltage is given by
VOUT = VR + VZ + (IBIAS)RX
A constant current flows through RY** because VOUT is constant, and small variations in IBIAS do not change practically the operating point of Vz. This situation is like constant current biasing of zener, which results in a very accurate setting of the zener voltage.
As long as VIN ; VOUT +2 volts, VOZ is constant thus current through RY is constant.
VOZ = VR + (IBIAS)Rx
Here the pin 2 of the regulator is raised above ground by Vz + (IBIAS)Rx. Thus, any combination of zener with a proper selection of RY can be used.
It is therefore necessary that VIN be so chosen that voltage between pins 1 and 2 of the IC does not exceed the maximum rating. Also, a high input-output differential voltage VIN-VOUT means more power dissipation in the series-pass element, the regulator. Thus, with proper selection of the input transformer voltage and capacitor, this should be minimized.
This circuit will have an excellent load and line regulation. For short-circuit
protection, it is recommended to use a fast-blow fuse of suitable value. Although the regulator has inherent short-circuit protection, the maximum current differs from device to device. Adequate heat sink should be used with the regulator.
For negative voltages, 79XX series regulators and ECN055 are used.
Some advantages of the circuits described above are: the lowest cost among comparable performance circuits, ability to work at low input-output differential voltages, and flexibility in design for various applications.
A microcontroller is also known as “computer on a chip,” billions of microcontroller units (MCUs) are embedded each year in a variety of products from toys to appliances to automobiles.
A microcontroller is a single chip that contains:
• Processor (or CPU)
• Non-Volatile memory for the program (ROM or flash)
• Volatile memory for input and output (RAM)
• Clock and an I/O control unit.
In other words, the processor, RAM, ROM, I/O PORTS AND TIMER are all embedded together on one chip. Therefore microcontrollers are ideal for many applications.
2.3.1 INTEL MCS -51
The Intel MCS-51 Harvard architecture single chip microcontroller (µC) series was developed by Intel in 1980 for use in embedded systems. Intel’s original versions were popular in the 1980s and early 1990s, but today it has been surpassed by a vast range of faster and functionally enhanced 8051-compatible devices manufactured by more than 20 independent manufacturers including:
• Infineon Technologies (formerly Siemens AG)
• Maxim Integrated Products ( Dallas Semiconductor subsidiary)
• NXP (formerly Philips Semiconductor)
• ST Microelectronics
• Silicon Laboratories
• Texas Instruments
• Cypress Semiconductor
Intel’s original MCS-51 family was developed using NMOS technology, but later versions, identified by a letter C in their name (e.g., 80C51) used CMOS technology which required less power than their NMOS predecessors. This made them more suitable for battery-powered devices.
2.3.2 IMPORTANT FEATURES AND APPLICATIONS OF 80C51
It provides following functions in a single package:
1. 8-bit ALU, Accumulator and 8-bit Registers; hence it is an 8 bit microcontroller.
2. 8-bit data bus
3. 16-bit address bus
4. On-chip RAM – 128 bytes (data memory)
5. On-chip ROM – 4K byte (program memory)
6. Four byte bi-directional input/output port
7. UART (serial port)
8. Two 16-bit Counter/timers
9. Two-level interrupt priority
10. Power saving mode (on some derivatives)
A particularly useful feature of the 8051 that made it popular in industrial control applications is the inclusion of a Boolean processing engine which allows bit-level Boolean logic operations to be carried out directly and efficiently on internal registers and RAM. Another valued feature is that it has four separate register sets, which can be used to greatly reduce interrupt latency compared to the more common method of storing interrupt context on a stack.
UART act as a serial communications interface. External pins can be configured to connect to internal shift registers in a variety of ways, and the internal timers can also be used, allowing serial communications in a number of modes, both synchronous and asynchronous. Some modes allow communications with no external components. A mode compatible with an RS-485 multi-point communications environment is achievable, but the 8051’s real strength is fitting in with existing ad-hoc protocols (e.g., when controlling serial-controlled devices).
Once a UART, and a timer if necessary, have been configured, the programmer needs only to write a simple interrupt routine to refill the send shift register whenever the last bit is shifted out by the UART and/or empty the full receive shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks.
The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle and have clock frequencies of up to 100 MHz, and are thus capable of an even greater number of instructions per second.
Common features included in modern 8051 based microcontrollers include
• Built-in reset timers with brown-out detection
• On-chip oscillators, self-programmable Flash ROM
• Boot loader code in ROM,
• EEPROM non-volatile data storage
• I²C, SPI, and USB host interfaces
• CAN or LIN bus
• PWM generators
• Analog comparators
• A/D and D/A converters
• RTCs, extra counters and timers
• In-circuit debugging facilities
• More interrupt sources, and extra power saving modes.
2.3.3 MEMORY ARCHITECTURE
The MCS-51 has four distinct types of memory – internal RAM, special function registers, program memory, and external data memory.
Internal RAM (IRAM) is located from address 0 to address 0xFF. IRAM from 0x00 to 0x7F can be accessed directly, and the bytes from 0x20 to 0x2F are also bit-addressable. IRAM from 0x80 to 0xFF must be accessed indirectly, using the @R0 or @R1 syntax, with the address to access loaded in R0 or R1.
Special function registers (SFR) are located from address 0x80 to 0xFF, and are accessed directly using the same instructions as for the lower half of IRAM. Some of the SFR’s are also bit-addressable.
Program memory (PMEM), though less common in usage than IRAM and XRAM, is located starting at address 0. It may be on- or off-chip, depending on the particular model of chip being used. Program memory is read-only, though some variants of the 8051 use on-chip flash memory and provide a method of re-
programming the memory in-system or in-application.
External data memory (XRAM) also starts at address 0. It can also be on- or off-chip; what makes it “external” is that it must be accessed using the MOVX (Move external) instruction. Many variants of the 8051 include the standard 256 bytes of IRAM plus a few KB of XRAM on the chip. If more XRAM is required by an application, the internal XRAM can be disabled, and all MOVX instructions will fetch from the external bus.
2.3.4 INSTRUCTION SET
The MCS-51 instruction set offers several addressing modes, including
1. Direct register, using ACC (the accumulator) and R0-R7.
2. Direct memory, which access the internal RAM or the SFR’s, depending on the address.
3. In-direct memory, using R0, R1, or DPTR to hold the memory address. The instruction used may vary to access internal RAM, external RAM, or program memory.
4. Individual bits of a range of IRAM and some of the SFR’s
Many of the operations allow any addressing mode for the source or the destination, for example, MOV 020h, 03fh will copy the value in memory location 0x3f in the internal RAM to the memory location 0x20, also in internal RAM. Because the 8051 is an accumulator-based architecture, all arithmetic operations must use the accumulator, e.g. ADD A, 020h will add the value in memory location 0x20 in the internal RAM to the accumulator.
One does not need to master these instructions to program the 8051. With the availability of good quality C compilers, including open source virtually all programs can be written with high level language.
2.3.5 PIN DESCRIPTION
VCC: Supply voltage
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI); Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.
Port 3 also receives some control signals for Flash programming and verification.
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
SPECIAL FUNCTION REGISTER (SFR) ADDRESSES:
ACC ACCUMULATOR 0E0H
B B REGISTER 0F0H
PSW PROGRAM STATUS WORD 0D0H
SP STACK POINTER 81H
DPTR DATA POINTER 2 BYTES
DPL LOW BYTE OF DPTR 82H
DPH HIGH BYTE OF DPTR 83H
P0 PORT0 80H
P1 PORT1 90H
P2 PORT2 0A0H
P3 PORT3 0B0H
TMOD TIMER/COUNTER MODE CONTROL 89H
TCON TIMER COUNTER CONTROL 88H
TH0 TIMER 0 HIGH BYTE 8CH
TLO TIMER 0 LOW BYTE 8AH
TH1 TIMER 1 HIGH BYTE 8DH
TL1 TIMER 1 LOW BYTE 8BH
SCON SERIAL CONTROL 98H
SBUF SERIAL DATA BUFFER 99H
TMOD (TIMER MODE) REGISTER
M1 M0MODE OPERATING MODE
0 0 0 13 BIT TIMER/MODE
0 1 1 16 BIT TIMER MODE
1 0 2 8 BIT AUTO RELOAD
1 1 3 SPLIT TIMER MODE
PSW (PROGRAM STATUS WORD)
PCON REGISATER (NON BIT ADDRESSABLE)
IE (INTERRUPT ENABLE REGISTOR)
INTERRUPT PRIORITY REGISTER
SCON: SERIAL PORT CONTROL REGISTER
2.3.6 MCS-51 FAMILY Instruction Set
Function: Absolute call
Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, op code bits 7-5, and the second byte of the instruction.
Description: ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a Carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands.
Function: Add with carry
Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary
Carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
Function: Absolute jump
Description: AJMP transfers program execution to the indicated address, which is formed at runtime by concatenating the high-order five bits of the PC (after incrementing the PC twice), op code bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP.
Function: Logical AND for byte variables
Description: ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is an accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data.
CJNE , , location
Function: Compare and jump if not equal
Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cleared. Neither operand is affected. The first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.
Function: Clear bit
Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Example: Port 1 has previously been written with 5DH (01011101B). The instruction CLR P1.2 will leave the port set to 59H (01011001B).
Function: Complement accumulator
Description: Each bit of the accumulator is logically complemented (one’s complement). Bits which previously contained a one are changed to zero and vice versa. No flags are affected.
Function: Decimal adjust accumulator for addition
Description: DA A adjusts the eight-bit value in the accumulator resulting from the
earlier addition of two variables (each in packed BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the accumulator producing the proper BCD digit in the low order nibble. This internal addition would set the carry flag if a carry-out of the low order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise.
Description: The variable indicated is decremented by 1. An original value of 00H wills underflow to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect.
Description: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared.
Function: Decrement and jump if not zero
Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H wills underflow to 0FFH. No flags are affected. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly
Description: INC increments the indicated variable by 1. An original value of 0FFH will overflow to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.
Function: Jump if bit is set
Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected.
Function: Jump if bit is set and clear bit
Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected.
Function: Jump if carry is set
Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding
the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.
JMP @A + DPTR
Function: Jump indirect
Description: Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the accumulator nor the data pointer is altered. No flags are affected.
Function: Jump if bit is not set
Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected.
Function: Jump if carry is not set
Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified.
Function: Jump if accumulator is not zero
Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified. No flags are affected. Example: The accumulator originally holds 00H.
Function: Jump if accumulator is zero
Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified. No flags are affected. Example: The accumulator originally contains 01H.
Function: Long call
Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64 Kbytes program memory address space. No flags are affected.
Function: Long jump
Description: LJMP causes an unconditional branch to the indicated address, by loading the high order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected.
Function: Move byte variable
Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed.
Description: It means to copy data from Register to Accumulator
Function: Move bit data
Description: The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected.
MOV DPTR, #data16
Function: Load data pointer with a 16-bit constant
Description: The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once.
Function: Move external
Description: The MOVX instructions transfer data between the accumulator and a byte of external data memory, hence the “X” appended to MOV. There are two types of instructions, differing in whether they provide an eight bit or sixteen-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provide an eight-bit address multiplexed with data on P0. Eight bits are sufficient for external l/O expansion decoding or a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins would be controlled by an output instruction preceding the MOVX. In the second type of MOVX instructions, the data pointer generates a sixteen-bit address. P2 outputs the high-order eight address bits (the contents of DPH) while P0 multiplexes the low-order eight bits (DPL) with data. The P2 special function register retains its previous contents while the P2 output buffers are emitting the contents of DPH. This form is faster and more efficient when accessing very large data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the output ports. It is possible in some situations to mix the two MOVX types. A large RAM array with its high-order address lines driven by P2 can be addressed via the data pointer, or with code to output high-order address bits to P2 followed by a MOVX instruction using R0 or R1.
Description: MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Example: Originally the accumulator holds the value 80 (50H). Register B holds the value 160 (0A0H). The instruction MUL AB will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the accumulator is cleared. The overflow flag is set, carry is cleared.
Function: No operation
Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected.
Function: Logical OR for byte variables
Description: ORL performs the bitwise logical OR operation between the indicated variables, storing the results in the destination byte. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data.
Function: Pop from stack
Description: The contents of the internal RAM location addressed by the stack pointer are read, and the stack pointer is decremented by one. The value read is the transfer to the directly addressed byte indicated. No flags are affected.
Function: Push onto stack
Description: The stack pointer is incremented by one. The contents of the indicated variable are then copied into the internal RAM location addressed by the stack pointer. Otherwise no flags are affected.
Function: Return from subroutine
Description: RET pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected.
Function: Return from interrupt
Description: RETI pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower or same-level interrupt is pending when the RETI
instruction is executed, that one instruction will be executed before the pending interrupt is processed.
Function: Rotate accumulator left
Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected.
Function: Rotate accumulator left through carry flag
Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected.
Function: Rotate accumulator right
Description: The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 positions. No flags are affected.
Function: Rotate accumulator right through carry flag
Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected.
Function: Set bit
Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected.
Function: Short jump
Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it.
Function: Subtract with borrow
Description: SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source operand). AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7 but not bit 6. When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes: register, direct, register indirect, or immediate.
Function: Swap nibbles within the accumulator
Description: SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four bit rotate instruction. No flags are affected.
Function: Exchange accumulator with byte variable
Description: XCH loads the accumulator with the contents of the indicated variable, at the same time writing the original accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing.
Function: Logical Exclusive OR for byte variables
Description: XRL performs the bitwise logical Exclusive OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be accumulator or immediate data.
2.4 PIR SENSOR
PIR sensors allow us to sense motion, almost always used to detect whether a human has moved in or out of the sensors range. They are small, inexpensive, operate at low-power. They don’t wear out and are easy to use. For that reason they are commonly found in appliances and gadgets that are used at homes or offices. They are often referred to as PIR, “Passive Infrared”, “Pyroelectric”, or “IR motion sensors.
PIRs are basically made of a pyroelectric sensor which can detect levels of infrared radiation. IR radiations are emitted by every object, at higher temperature more radiations are emitted. The sensor when used as a motion detector, it contains two halves. The reason for that is that we are looking to detect motion or more accurately change and not average IR levels. The two halves are wired up so that they cancel out each other. If one half sees more or less IR radiation than the other, the output will swing high or low.
Along with the pyroelectric sensor is a bunch of supporting circuitry, resistors and capacitors. It seems that most small hobbyist sensors use the BISS0001 (“Micro Power PIR Motion Detector IC”) chip which is not expensive. This chip takes the output of the sensor and does some minor processing on it to emit a digital output pulse from the analog sensor.
For many basic projects or products that need to detect when a person has left or entered the area, or has approached, PIR sensors are immensely used. They have a wide lens range and are easy to interface with microcontroller. PIR sensors merely sense motion and are not used to count the number of people that are around or to
estimate their distance from the sensor, the lens is often fixed to a certain sweep and distance.
How does it work?
PIR sensors are more complicated when compared to many other sensors because there are multiple variables that affect the sensors input and output. The PIR sensor itself has two slots in it, each slot is made of a special material that is sensitive to IR radiations. When the sensor is idle, both slots detect the same amount of IR, the ambient amount radiated from the room or walls or outdoors. When a warm body like a human or animal passes by, it first intercepts one half of the PIR sensor, which causes a positive differential change between the two halves. When the warm body leaves the sensing area, the reverse happens, whereby the sensor generates a negative differential change. These pulses are detected .
The IR sensor is housed in a hermetically sealed metal can to improve immunity to noise, temperature and humidity. There is a window made of IR-transmissive material, typically coated with silicon, that protects the sensing element. Behind the window are the two balanced sensors.
Figure shows the element window and the two pieces of sensing material with their standard dimensions.
The above image shows the internal schematic of a PIR sensor. It contains JFET (a type of transistor) which causes very low-noise and buffers the extremely high impedance of the sensors into something a low-cost chip (BIS0001 chip) can sense.
PIR sensors are rather generic and for the most part vary only in price and sensitivity. Optics forms the basis of the sensor. The lens costs only a few cents and can change the breadth, range and sensing pattern.
In order to have a large detection area, a simple lens is used such as those found in a camera. They condenses a large area (such as a landscape) into a small one (on film or a CCD sensor). For some technical reasons the PIR lenses are made small, thin and moldable, even though it may add distortion. For this reason the sensors are actually Fresnel lenses. The Fresnel lens condenses light, providing a larger range of IR to the sensor.
CHAPTER 3: PROTOTYPE DEVELOPMENT
Design a frame
Design a circuit
Design and Run
Burning Codes in
1.Start software Keil uVision.
2.Go to Project ? New uVision Project.
3.Select any target location to create and save project.
4.Select the microcontroller to be used ( here we have used at89s52 ).
5.Change XTAL frequency to 11.0592MHz.
6.Go to OUTPUT tab and check CREATE.HEX file box.
7.Add assembly file to the Source Group.
8.Write code in assembly language.
9.Now Build it and check for Error(s).
led1 equ p2.0
pir equ p2.1
buz equ p2.6
mpos equ p2.2
mneg equ p2.3
kpos equ p2.4
kneg equ p2.5
;ORG 0000H ;RESET OPERATION
;ORG 0003H ;EXTERNAL0 INTERRUPT
;RETI ;RETURN FROM THE INTERRUPT
;ORG 000BH ;TIMER0 INTERRUT
;ORG 0013H ;EXTERNAL1 INTERRUPT
;ORG 001BH ;TIMER1 INTERRUPT
;ORG 0023H ;SERIAL COMMUNICATION INTERRUPT ;RETI
MOV SP,#70H ; Move the stack pointer at 70h location
MOV IE,#00H ; Disable all the interrupts
MOV IP,#00H ; Dissable the interrupt priority register
MOV P0,#0FFH ; Move 0FFH in in port 0
MOV P1,#0FFH ; Move 0FFH in in port 1
MOV P2,#0FFH ; Move 0FFH in in port 2
MOV P3,#0FFH ; Move 0FFH in in port 3
The robot is carried to the disaster area and mounted. The batteries must be charged totally before the operation. The camera (if used) must be synchronized with a cell phone over Wi-Fi and the cell phone must be placed in the holder on the remote controller. Then the robot is powered on and the operator manually drives the robot inside the disaster area. The movements of robot is controlled using a mobile. The robot is then moved to the vicinity to search for casualties. To enable human detection the robot is stopped and checked for any human detection looking at the red led. Buzzer will sound on finding a human casualty and LED will get ON. PIR sensor can detect humans within 4-5 meters. Then the robot is manually driven to that area to look closer. If the lighting conditions are poor, the power led is enabled for extra lighting. The operator rotates the device and the camera to see the surrounding details. The team makes a consideration plan and enters the disaster area to rescue the victims.
CHAPTER 4: CONCLUSIONS AND FUTURE WORK
1.This system is effective and safe and it can ensure that there are no humans left behind in a rescue operations.
2.This system is accurate and reliable.
1. Battery backup is weak which can be overcome by using a solar panel.
2. The initial cost may be high if very high range sensors are being used for commercial purposes
4.3 FUTURE DEVELOPMENTS
1.System can be further developed inorder to maintain the count of people saved and count of casualities.
2.This device may be improved by using high range sensors (Laser, ultrasound or powerful thermal cameras), GPS, and motors of high capacity.